ASIC Verification Engineer
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- Full-time
- Hybrid
- Work permit not stated
ASIC Verification Engineer role on the Optical Networks team, working as an independent contributor or leading a team on SoC/FPGA verification.
Requires a Bachelor's degree in CS/EE and minimum 8+ years of ASIC verification experience, plus SystemVerilog/UVM and Python.
Location is listed as Canada with CAD base salary of 94,702.22 to 145,582.22 plus other benefits; the posting does not state work authorization, workplace arrangement or hybrid days.
From the posting
- employment types
ATS employment type: full_time
- workplace
ATS workplace type: hybrid
- locations
ATS location: Canada
- salary
Salary CAD Base 94,702.22 to 145,582.22 plus other potential benefits
- seniority
Minimum 8+ years of relevant experience in the ASIC verification field.
- job function
ASIC Verification Engineer
- role family
ASIC Verification Engineer
- skills
Fluent in System Verilog and scripting languages such as Python.
- skills
Must have intimate knowledge of UVM methodology.
- skills
Knowledgeable about assertions and functional coverage Experience with code coverage and formal verification tools
- skills
Knowledge of DSP and/or FEC will be desirable.
- years experience min
Minimum 8+ years of relevant experience in the ASIC verification field.
- education required
Bachelor's degree in CS/EE is required.
- actionable
Working as independent contributor in development and verification of the world leading SoCs based on latest technology ASICs and FPGAs
Job description
We are seeking an ASIC Verification Engineer with a solid ASIC/FPGA verification test strategy & development and debugging skills."The Network Infrastructure group is at the heart of a revolution to connectivity, pushing the boundaries to deliver more and faster network capacity to people worldwide through our ambition, innovation, and technical expertise. Join Optical Networks division, where innovation meets scale in the AI-driven data center era. With the recent acquisition of Infinera, we’ve united two industry leaders to create an optical networking powerhouse—combining cutting-edge technology with proven leadership to redefine the future of connectivity.
Responsibilities
- Working as independent contributor in development and verification of the world leading SoCs based on latest technology ASICs and FPGAs
- Working on System Verilog/UVM-based protocol/traffic generators/checkers
- Working on test plan based on functional requirements as well as applicable standards requirements
- Working with experts of different areas to ensure the most competitive solutions
- Cooperating with system engineers, HW/SW development, suppliers and other relevant functions to solve technical issues
- Supporting HW/SW bring-up and debug
- Work as an independent contributor or lead a team to deliver defined tasks.
Qualifications
- Masters degree desired, Bachelor's degree in CS/EE is required.
- Minimum 8+ years of relevant experience in the ASIC verification field.
- Should have worked on developing/implementing test plans at the block or sub-chip levels for complex ASICs.
- Fluent in System Verilog and scripting languages such as Python.
- Must have intimate knowledge of UVM methodology.
- Knowledgeable about assertions and functional coverage Experience with code coverage and formal verification tools; familiarity with evolving verification methodologies.
- Strong problem solving skills.
- Very good communication skills and ability and desire to work in a geographically diverse team environment.
- Will be responsible for the definition, development, and execution of self-checking tests for complex digital ASICs.
- Knowledge of DSP and/or FEC will be desirable.
Seen on
- oraclecloud — fa-evmr-saasfaprod1.fa.ocs.oraclecloud.com